The present invention relates to a semiconductor programmable memory device, and especially to an electrically erasable programmable read only memory (abbreviated as EEPROM or E.sup.2 PROM) device. The present invention is directed to a circuit configuration which reduces the time required to check the performance of the E.sup.2 PROM.
A semiconductor memory device is tested by writing a predetermined pattern, such as a checkerboard pattern, in its memory matrix, and reading it out. The checkerboard pattern is composed of "1"s and "0"s written alternately in each of the memory cells, and as a whole, the memory matrix is patterned like a checkerboard.
The read out process of an E.sup.2 PROM is performed very quickly, however, the writing process into a memory cell of the E.sup.2 PROM takes a long time. For example, it takes approximately 10 ms to write or erase a byte, so that it takes more than a minute to "write" the checker pattern in a 64 k-bit E.sup.2 PROM. Therefore, as the memory size becomes large, the time required to write in a checkerboard pattern (and hence the testing time) becomes very long.
In order to clearly disclose the advantages of the present invention, the structure and working process of a prior art E.sup.2 PROM will be described briefly. FIG. 1 shows schematically a cross-sectional view of a memory transistor used in a memory cell of an E.sup.2 PROM. S and D indicate, respectively, a source and drain of an n-channel floating gate memory cell, CG is a control gate, and FG is a floating gate. In the E.sup.2 PROM, when electrons are accumulated in the floating gate FG, the memory transistor is cut off. This process is called an "erase" operation and a datum "1" is written in the memory cell. When the electrons are discharged from the floating gate FG, the memory transistor switches to an ON state. This process is called a "write" operation, and a datum "0" is written in the memory cell.
In the structure of the memory cell of FIG. 1, the isolation layer IL between the floating gate FG and the drain D is fabricated very thin. Thus, electrons can pass through the isolation layer IL, due to the tunnel effect, when a high voltage is applied between the floating gate FG and the drain D. In order to perform the "erase" operation in a memory cell, a high voltage Vpp (21 volts for example) is applied to the control gate CG, and the voltage of the drain D is kept at 0 volts. The voltage of the floating gate FG is increased due to a coupling capacity between both gates and, therefore, electrons are injected from the drain D into the floating gate FG by the tunnel effect, and a datum "1" is written in the memory cell.
In order to perform the "write" operation, the voltage of the control gate CG is kept at 0 volts, and a high voltage Vpp is applied to the drain D. As a result, the electrons on the floating gate FG are discharged to the drain D by the tunnel effect, and a datum "0" is written in the memory cell.
FIG. 2 is a circuit diagram of a conventional E.sup.2 PROM for showing a process relevant to the present invention. A fundamental process for writing data in the memory cells of a prior art E.sup.2 PROM device will be explained briefly with reference to FIG. 2. The description will be given, as an example, with respect to a memory matrix with a byte made up of 8 bits. In the figure, word lines WL1, WL2 . . . WLn are arranged in a horizontal direction, and bit lines BL are arranged in a vertical direction. At each cross point of the word lines and the bit lines, a memory cell 2 is provided. Each of the memory cells 2 includes a memory transistor having a floating gate, and a MOS-FET (metal-oxide-semiconductor type field effect transistor). Each eight memory cells on a word line form a memory array 1 for one byte composed of eight bits.
In order to control the eight memory cells of each byte, a gate-controlling transistor 4 is provided to each memory array 1. Gate-controlling transistor 4 controls the voltage of the control gates of each memory transistor. The gate of each gate-controlling transistor 4 is also connected to the respective word line of the memory array which it controls.
As can be seen in FIG. 2, the memory arrays 1 are arranged in several columns, and data input lines Di1, Di2 . . . Di8 are connected in parallel to each column and include the bit lines BL. On each of the bit lines BL is provided a transistor 3. The gates of the transistors 3 in each column are connected to each other. The group of transistors 3 corresponding to each column form respectively the Y-gates Y1, Y2 . . . Yn. In the description hereinafter, the control signals to control the gates of the columns which are controlled by these gates are also referred to as control signals Y1, Y2 . . . Yn. A built-in cell reference circuit 5 provides reference voltages of 0, 21, and 2 volts respectively for the write, erase, and read operations. These reference voltages are supplied to the gate-controlling transistors 4 via the transistors 3, for controlling the control gates of the memory transistors.
In the circuit configuration of FIG. 2, a specific byte is identified by the cross point of the column and word line where it is located, and the byte is selected by applying a control signal to the transistors 3 and 4 corresponding to the specific byte, to make them conductive. A fundamental process to erase and to write in the memory matrix will be explained with reference to FIG. 2.
In order to "erase" a specific byte (Y1, WL1) for example, the output voltage of the cell reference circuit 5 is increased to a high voltage Vpp, and the voltage of the bit lines is kept to 0 volts. By doing so, the high voltage Vpp is applied to the control gates of the memory transistors in the specific byte (Y1, WL1), and the drain voltages of them become 0 volts. Thus, these memory transistors begin the "erase" operation, which has been previously described with respect to FIG. 1, and "1" is written in each of the memory cells of the byte (Y1, WL1).
In order to "write" the specific byte (Y1, WL1) for example, the Y-gate Y1 and the word line WL1 are selected, the output voltage of the cell reference circuit 5 is decreased to 0 volts, and the voltage of the bit lines is increased to Vpp. Then the memory transistors of the specific byte begin the "write" operation as has been described before, and "0" is written in each of the memory cells of the byte (Y1, WL1).
As previously mentioned, in order to test the programmable ROM (read only memory), a checkerboard pattern is written in the memory matrix. Each ROM device integrated in an IC (integrated circuit) is provided with contact pins corresponding to each of the data input lines, but the number of word lines is too great to provide the IC with discrete input terminals. Therefore, only one contact pin is provided for the word lines. The selection of the word lines is done by applying a code to the word pin. Then, a decoder provided in the IC selects the word line according to the code (address) allotted to each of the word lines. Therefore, it is necessary to write, one by one, the data of the checkerboard pattern in all of the bytes. For example, in a 64 k-bit memory device of 8 bits/byte, there are 8,192 memory arrays to be written. Therefore, if it takes 10 ms to write a byte, it requires approximately 82 sec. to write a checkerboard pattern in the device. This length of time, and hence the time required to test a device, increases as the memory size of the device increases. It is therefore a serious problem for manufacturers of memory devices.
Some attempts to decrease the test time have been proposed. An example is disclosed in Japanese Patent No. 56-50357, Nov. 28, 1981, by M. Higuchi et al. Higuchi et al. provides plural decoders in a device, which results in only a slight decrease in the test time.